1. Technical Field
The present invention relates in general to computer memory components and in particular to reading data from computer memory components. Still more particularly, the present invention relates to a method and memory array circuit design for obtaining predictable array output when an invalid address is requested from a memory component.
2. Description of the Related Art
Computer memory components, e.g., random access memory (RAM) and read only memory (ROM), are designed with arrays that are subdivided into a number of address lines that hold data. Each line is capable of holding a certain amount of data based primarily on the size of the line. The total number of lines is typically a power of two (i.e., 2N, where N=1, 2, . . . ). The address of the line is utilized to find and access stored data when the data is desired to be read from memory.
During development of a memory array, the memory chip is made to undergo a series of logic test to ensure that data is being read correctly. During the logic tests of a read-only memory (ROM) array, the array is sent random addresses and is expected to give a predictable output. When a valid address is read, the output is predicted to be the data in that address, and the control logic circuitry of the memory array is reset for the next data access.
If the number of word lines contained in the array is not a power of two, there will be some addresses that are xe2x80x9cinvalidxe2x80x9d. An invalid address occurs whenever a memory array has more address space than array space. Attempts to read an address that does not contain valid data often proves to be problematic because the result is not predictable. This problem occurs irrespective of if the arrays are ROMs or RAMs. Thus, during the logic test, whenever the random address generator selects these invalid addresses to send to the memory component, there are no corresponding word lines from which data may be provided; however, the memory array still needs to provide a predictable output for the logic test and also has to have its control logic circuitry reset for the next data access.
Some memory array designs decode the invalid address and directly put predicable data in the data out latches. With these designs/methods, however, if an invalid address is incorrectly decoded as a result of skew or a glitch, etc., the read will be ended before the array can correct the data. This ultimately degrades the setup time as illustrated in the timing diagram of FIG. 1A.
Other designs map the invalid address(es) into valid address spaces. However, address mapping is not always possible, particularly on memory arrays with certain pre-decode addressing schemes that are optimized for performance. FIG. 1C illustrates the example timing diagram for such designs.
A third ROM design handles invalid addresses by ignoring them. No data out latch is updated and no circuitry is reset. The ROM waits for the next valid address to be clocked into the chip as shown in the sample timing diagram of FIG. 1B. This is achieved at the expense of performance. An address latch is used that is normally closed and only opens briefly after a clock signal falls in order to capture a new address. A performance-oriented design requires the latch to be normally open and closes immediately upon falling of the clock signal. An internal reset is required at the end of operation to re-open the address latch.
The present invention recognizes that it would therefore be advantageous and desirable to have a memory system design and method that enables the utilization of any address pre-decoding and still efficiently and correctly handle invalid addresses. A method and memory system design that prevents a partially decoded address from being interpreted as invalid and resetting the array prematurely would be a welcomed improvement. These and other benefits are provided by the present invention.
Disclosed is a method and memory circuitry design for efficiently obtaining predictable array output when an invalid address is requested. The memory circuit design comprises an invalid word line path in addition to the standard valid word line path. In order to provide correct output, a dummy word line output of a first decode logic is delayed and the delayed dummy word line output is ANDed with a word line output to update the data out latch. Further, the invalid word line output of a second decode logic is also delayed, and the delayed invalid word line output is ORed with the delayed dummy word line output to reset the control logic. ORing the delayed signals allows the predictable output to be provided at a same clock time, irrespective of whether a valid address or an invalid address is decoded.
In the preferred embodiment, maintaining similar clock times for valid and invalid addresses is completed by running the invalid word line path parallel to the dummy word line path. Also, both line paths are run on the perimeter of the memory array to allow for scaling as the array increases or decreases in size.
The method of the invention is different from the prior art because it uses an auxiliary address path to achieve a similar cycle time as a normal array read. Further, when an invalid address is requested, the chip does not xe2x80x9changxe2x80x9d and is made ready for the next read. When an invalid address is requested, the chip produces predictable data on the output latches and is ready for the next read.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.